Synchronous sequential circuits or synchronization circuits are integrated logic circuits in which changes in a system state and an output signal are directly initiated by a discrete docking signal. Synchronization circuits can be employed in a wide variety of digital logic designs such as, for example, programmable controllers, microprocessors, and other digital applications. Such integrated circuits typically receive an input signal from an external device and execute one or more processing operations in order to generate an output signal. A clock signal controls the flow of the input signal with respect to the synchronization circuit. A delay-timing signal such as, for example, cell delay timing and wire delay timing with respect to the synchronization circuit, may affect the functionality of the digital logic designs.
A gray code counter can be adapted in the context of digital logic designs in order to produce a single bit transition within a specific window and generate a virtually error free counter signal. A gray code counter provides a relatively simple decoding operation with a decoded output. FIG. 1 illustrates a timing model of a prior art n-bit gray counter circuit 100. The circuit 100 depicted in FIG. 1 generally includes a set of source flip-flops 120, a set of destination flip-flops 140 that are operatively configured with a gray encoder 110 and a gray decoder 150. A source clock (Cs) drives the source flip-flops 120 in order to generate a gray code signal in the circuit 100. The gray code signal can be placed into a block and/or die such as a gray code block 130 of the circuit 100. Similarly, a destination clock (Cd) drives the destination flip-flops 140.
A clock insertion tool capable of inserting the trees into the circuit 100 can be adapted to permit the data bits of the gray code signals at the destination flip-flops 140 within a certain timing window. The timing window with respect to different data bits between the source flip-flops 120 and the destination flip-flops 140 can be provided by a difference of travel time between the outputs of the source flip-flops 120 and the inputs of the destination flip-flops 140. The flip-flops 120 and 140 must be positioned together and the timing signals in the circuit are to be routed with a special attribute in a layout phase of the circuit design. Additionally, an invalid transition in the gray counter circuit 100 may cause an invalid state transition (e.g., an out of order state) with respect to the digital logic design. Table 1 shown below represents the transitions between a three-bit binary code sequences to a three-bit gray code utilizing the gray code counter 100.
TABLE 1Valid Operation:010 => 110, 110 => 111010 => 111Invalid Operation:010 => 011 (T2 before T1)
For example, if the transition ‘T2’ occurs before a transition event ‘T1’, then the gray code counter may enter an invalid transition state (e.g., a ‘011’ state) for at least one destination clock cycle. The transitions in the synchronization circuit 100 must be produced in a limited timing window in order to effectively synchronize the asynchronous clock domains. Additionally, such prior art approach for implementing the flip-flops in the synchronization circuit can be a time consuming process and requires additional verification with respect to the timing window.
Based on the foregoing, it is believed that a need exists for an improved system and method for eliminating implementation timing with respect to a synchronization circuit, as described in greater detail herein.